Amkor has developed an innovative Silicon-Less Integrated Module packaging technology call SLIM™. This SLIM™ chip packaging technology leverages the 2.5D sub-micron routing capability and no TSV is required, which lowers cost and improves electrical performance.


  • TEOS and polymer based dielectrics
  • Multi-die capability
  • Interconnection density down to submicron if required
  • Cu pillar die interconnect down to 30 μm pitch
  • 3D/Package-on-Package (PoP) capability utilizing Thru Mold Via (TMV®) or tall Cu pillars

Package Technology Integration Roadmap

SLIM™ target applications are multi-die products for high performance applications. The key feature is the ability to route these designs using Cu Back End of Line (BEOL) layers, which can support submicron line and spaces and 1 μm via sizes. For the mobile space, the final package construction is considered a wafer scale package which is attached directly to the end product circuit board.

SLIM™ Technology vs. 2.5D TSV Interposer The roots of SLIM™ innovation were forged during the 2.5D TSV-bearing interposer package development. SLIM retains the best features of the 2.5D multi-die interposer approach, and further optimizes the cost and electrical performance.

Through Silicon Via (TSV) interconnects are becoming an integral part of the high performance IC packaging landscape. TSVs have enabled high bandwidth stacked DRAM memory (HBM), and in turn the HBM performance and dissipated-power performance points have enabled product designs with higher performance levels than ever before. TSV bearing products enable a vast array of multi-die combinations with new performance levels, SOC-splitting economics for mixed silicon process notes and heterogeneous die combinations not before achievable.

The signal routing resources available for multi-die implementation are unparalleled, with fine line damascene Cu Back End of Line (BEOL) typical of a 65 nm Cu back end. The TSVs are required to provide a suitable Power Deliver Network (PDN) and I/O signal vias for off?package I/Os.

The objective of SLIM is to keep the fine line routing resources while removing the TSV. This can provide a lower total cost than TSV-bearing interposers, and some specific electrical performance improvements as well.

Comparison of SLIM™ vs. 2.5D TSV Interposer

 SLIM vs TSV Comparision

Package Technology Integration Roadmap

SLIM Roadmap

The SLIM high level construction is shown compared to a typical 2.5D TSV construction in the previous figure. The primary mechanical feature of the SLIM construction is the lack of the TSV. The TSV is not in the electrical path from the top die to the C4, which can have electrical benefits, as outline below. The bulk silicon has been removed from the interposer, so that only the thin-film metal and dielectric layers present in the BEOL construction are retained. The connection to these BEOL metal layers is provided by Amkor using process technology developed for the 2.5D TSV.

SLIM™ Package Assembly Flow

The end result is a very thin package, fabricated using a truncated process flow from a 2.5D production line. The figure below shows a high level process flow the SLIM product. Key steps not required are CVD deposition of inorganic dielectrics and CMP processing.

SLIM™ Technology Process Flow

SLIM Process Flow

Advanced Wafer Product Positiioning

SLIM Positioning

For more information on our Silicon-Less Integrated Module packaging technology (SLIM™), please contact an Amkor Regional Sales Office near you or fill out the Request Form.