Amkor had introduced a new, state-of-the-art fan-out structure called Silicon Wafer Integrated Fan-out Technology (SWIFT®) to bridge the gap between TSV and traditional WLFO/FOWLP packages. SWIFT technology is designed to provide increased I/O and circuit density within a reduced footprint and profile for single & multi-die applications. The distinctive characteristics of SWIFT technology are due, in part, to the fine feature capabilities associated with this innovative wafer-level packaging technique. This allows much more aggressive design rules to be applied compared to traditional WLFO and laminate-based assemblies. In addition, SWIFT technology enables the creation of advanced 3D structures that address the need for increased IC integration in emerging mobile and networking applications.

SWIFT Structure and Attributes


The figure below shows cross-section illustrations of a single die SWIFT and dual-die 3D/Package-in-Package (PoP) SWIFT structures. Although the package appears to be of a typical fine-pitch flip chip construction, it incorporates some unique features not associated with conventional IC packages.

These unique SWIFT features include:

  • Polymer-based dielectrics
  • Multi-die and large die capability
  • Large package body capability
  • Interconnect density down to 2 μm line/space (critical for SoC partitioning applications)
  • Cu pillar die interconnect down to 30 μm pitch
  • 3D/Package-on-Package  capability utilizing Thru Mold Via (TMV®) or tall Cu pillars
  • Meets JEDEC MSL3 CLR and BLR requirements

 

SWIFT Enabling Technologies


Key assembly technologies enable the creation of these distinctive SWIFT features and attributes. Through the use of stepper photo imaging equipment, 2/2 μm line/space features can be achieved, enabling very high density die-to-die connections required for SoC partitioning and networking applications where 2.5D TSV would typically be used. Fine-pitch die micro bumps provide a high-density interconnect for advanced products, such as application processors and baseband devices. In addition, tall Cu pillars enable a high density vertical interface for mounting advanced memory devices on the top of the SWIFT structure.

SWIFT Enabling Technologies


SWIFT Reliability Data

SWIFT Process Flow


These SWIFT attributes are realized by applying a unique process flow that incorporates both flip chip assembly and wafer-level processing techniques, as shown below.

SWIFT Technology Process Flow

SWIFT Process Flow

Advanced Wafer Product Positioning

SLIM Positioning

For more information on Silicon Wafer Integrated Fan-out Technology (SWIFT®), please contact an Amkor Regional Sales Office near you or fill out the Request Form.

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