Copper (Cu) pillar bump is a next generation flip chip interconnect offering advantages in many designs while meeting current and future ROHS requirements. Interconnect choice for Transceivers, Embedded Processors, Application Processors, Power Management, Baseband, ASICs and SOCs when combinations of fine pitch. ROHS/Green compliance, low cost and electromigration performance are required.
The above plot shows improvement in life for Copper Cu pillar over SnAg bump for the same current/temperature condition and similar bump/UBM geometry. No failure was observed in Cu Pillar Bump even after 8000 hours of testing at the same condition with no failures.
|Test||Test Conditions||Read Point||SS||Results|
|MSL3||30 / 60-192||260C 3X||77 x 12 lots||PASS|
|T/C B||-55°C / 125 °C||1000X||77 x 3 lots||PASS|
|HAST||130°C / 85% RH||96 hrs||77 x 3 lots||PASS|
|T&H||85°C / 85% RH||1000hrs||77 x 3 lots||PASS|
|HTS||150°C||1000hrs||77 x 3 lots||PASS|