Copper (Cu) pillar bump is a next generation flip chip interconnect offering advantages in many designs while meeting current and future ROHS requirements. Interconnect choice for Transceivers, Embedded Processors, Application Processors, Power Management, Baseband, ASICs and SOCs when combinations of fine pitch. ROHS/Green compliance, low cost and electromigration performance are required. 

Copper Pillar Overview

Copper pillar platform

  • Fine pitch CSP
  • Area array fine pitch fcBGA
  • µBump: F2F, TSV

Production status

  • +300M units shipment since 2010
  • Copper, Lead Free and Copper/Ni/Lead Free
  • 14nm in production

Package structure

  • Bare die CSP/PoP, Molded PoP/TMV, TSV, FCBGA

Copper Pillar Bump Design Rules

Copper Cu Pillar Bump Design
Cu Pillar Diameter (D) 20 - 50 μm
Total Height (TH) 30 - 60 μm


Pad Design Guidelines

Copper Cu Pillar Pad Design

General Design Rules 60
45 / 90
40 / 80
30 / 60
(A) Row to Row Pitch N/A N/A 90 80 60
(B) Bond Pad Width 30 25 22 20 TBD
(C) Trace Pitch 60 50 45 40 30


Electromigration Reliability Comparison of Cu Pillar with SnAg Bump

Copper Cu Pillar Comparison

The above plot shows improvement in life for Copper Cu pillar over SnAg bump for the same current/temperature condition and similar bump/UBM geometry. No failure was observed in Cu Pillar Bump even after 8000 hours of testing at the same condition with no failures.

SQB Results

Test Test Conditions Read Point SS Results
MSL3 30 / 60-192 260C 3X 77 x 12 lots PASS
T/C B -55°C / 125 °C 1000X 77 x 3 lots PASS
HAST 130°C / 85% RH 96 hrs 77 x 3 lots PASS
T&H 85°C / 85% RH 1000hrs 77 x 3 lots PASS
HTS 150°C 1000hrs 77 x 3 lots PASS

For more information on our Cu Pillar offerings, please contact an Amkor Regional Sales Office near you or fill out the Request for Information Form.


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