Description	File Type	File Size
3D Electrical Modeling Software and Data FAQ		50 kb

Q1: A trace in a package and PCB may be expected to carry specific current density without significant heating or voltage drop. What is relation between current density and trace structure such as trace width and trace thickness?

A1: Handling large currents with insufficient copper in a trace may result in a voltage drop, significant heating (increase in temperature) and degrades circuit performance. The following figure illustrates relation among maximum current density, trace structure, and temperature rise.

Q2: How does the bond wire diameter reduction affect the electrical performance of a package?

A2: The current trend in semiconductor towards sub-micron technology has increased the density of logic circuits in smaller die sizes. The number of I/Os is increased. Consequently, the pad pitches have reduced. This reduction required thinner bond wires for proper bonding. In order to estimate the effect of bond wire diameter reduction, four sets (0.8mils, 1.2 mils and 1.3 mils) have been analyzed by using a powerful EM simulator. The results obtained from this analysis as well as the percentage of change in each of the cases is reported in the Table 1 and figures 1.1a, 1.1b, 11d, and 1.1d. These data indicate significant increase in wire resistance and up to 10 % increase in the wire inductance. Insignificant effect has been observed in the capacitance and inductance coupling.