The electrical and mechanical connection between a die and substrate is one of the most critical elements of any flip chip package structure. Predominantly lead-tin and lead-free solders at the present time, these connections, or bumps must exhibit superior adhesion to the die, minimal resistance, and result in high assembly yields. Solder bumps are formed using either thin film metal deposition or ball loading techniques.

Amkor offers state-of-the-art capability in electroplated solder technologies in multiple strategic locations (Taiwan, Korea, Singapore, and the US). These locations are uniquely situated adjacent to major foundry sources to enable our customers reduced time to market with integrated factory logistics.

Our Singapore operation began high volume production of electroplated bumping on 300mm wafers in October 2006. The Singapore facility also offers turnkey probe and test facilities for its customers.

Our Taiwan facility is a world-class solder bumping line with HVM production capability for 200 mm and 300 mm wafers. High lead, eutectic, and lead-free solder compositions (all low alpha) are production certified. In addition, the facility offers repassivation, single and multi-layer redistribution processes for both flip chip and wafer level chip scale package applications.

Our Korea and Taiwan bumping operations are co-located with wafer probe, assembly and final test, enabling Amkor to provide complete “Turnkey” flip chip and WLCSP solutions in these key geographic locations. These facilities offer economy of scale as WLCSP continues to grow in the future. This combination of technology and manufacturing capabilities is unparalleled in the subcontract manufacturing industry.

Our facility in North Carolina is primarily focused on technology development. North Carolina offers a full range of plated solders, integrated passives on die, and Cu pillar bumping. In addition to these offerings, through silicon via (TSV) development is managed from this location.

Bumping Process Specifics

Amkor’s bumping process is production certified through the full package size range from WLCSP, up through SuperFC^®.

Wafer Size:	150 mm - 300 mm
Solder Compositions:	63Sn/37Pb, 95Pb/5Sn, 97.5Sn/2.5Ag (all available as low alpha: <0.02 cts/hr/cm2), SnAgCu
Pad Pitch Lower Limit:	85 µm
Typical Production Bump Height:	200 µm array: 90 µm 125 µm peripheral: 75 µm
Repassivation Coatings:	Polyimide, BCB
Redistribution Materials:	Copper

Related Processes / Services

Wafer Bumping and Wafer Level Chip Scale Packaging (WLCSP) use many of the same basic process steps in production. Key WLCSP developments have resulted in improved wafer level technology known as CSPnl™. CSPnl™ combines plated copper technology and advanced photopolymers to produce the industry’s most robust wafer level solutions. CSPnl™ is available down to 0.4 mm pitch and supports a range of solder volumes to meet customer requirements.

Closely related to both bumping and WLP production is "die processing" capability, which consists of process steps that transform either bumped or WLCSP product from wafer form into die form. Die processing typically involves test, singulation, inspection, and pick-and-place, and Amkor offers these full turnkey services to support our customers at multiple facilities around the world. Die processing is supported globally in the US, Taiwan and Korea to deal with any possible supply chain scenario.

Technology Development

Amkor maintains strong initiatives in the area of technology development to further support customers’ future needs. Continuous improvement programs are in place to optimize and cost-reduce the wafer bumping processes.

• Electroplating capabilities will support fine pitch (< 85 µm) bumping, copper pillar structures, and “passive integration”
• Higher performance polyimide materials
• WLCSP die size support to greater than 144 I/O’s