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Flip Chip CSP (fcCSP)
Amkor Technology is now offering the Flip Chip CSP (fcCSP) package -- a flip chip solution in a CSP package format. This package construction utilizes eutectic tin / lead (63Sn / 37Pb) flip chip interconnect technology, in either area array or peripheral bump layout, replacing standard wire-bond interconnect. The advantages of flip chip interconnect are twofold: it provides enhanced electrical performance over standard wirebond technology, and it allows for a smaller form factor due to increased routing density, the ability to use area array die bumps and the elimination of wire-bond loops. Current wafer bump technology and flip chip assembly process allows for a minimum of 150 µm peripheral flip chip bumping, or 250 µm area array bumping.
The fcCSP is based on Amkor's proprietary ChipArray® BGA (CABGA) package construction, using cutting edge thin core laminate substrates. The package is assembled in strip format, gang molded and saw singulated for manufacturing efficiency and cost minimization. Laser ablated solder mask technology, via-in-pad substrate structure, and thin core substrate panel processing allow for increased routing density and enhanced electrical performance, making the fcCSP an attractive option for advanced CSP applications where electrical performance is a critical factor.
The fcCSP is available in both thin core laminate substrate technology, as well as ceramic substrate technology. Package size ranges from 3 mm to 15 mm, accommodating BGA ball pitches from 0.5 mm to 1.0 mm. In addition to BGA technology, the fcCSP is also available in LGA format, allowing for a lower minimum package thickness.
The Ceramic flip chip package provides maximum flexibility for designers for number of layers and routing. Current production is from 300 - 1800 I/O in LGA, BGA or SCI (solder column interposer) formats, 1.27 mm and 1.0 mm pitch. AlSiC lids can be attached for maximum thermal dissipation.
fcBGA (Flip Chip BGA): Moderate routing density, lowest cost flip chip package in intermediate ball counts. Bare die or Single Piece Lid. Qualified with both BU and 4L thin core substrates. Ball Count range is 256 - 1900 and Body Size range is 17 - 45 mm.
Ceramic fcBGA (Ceramic Flip Chip BGA): Alumina or HiTCE flip chip packages with BGA, LGA, or SCI interconnect format. Capability for high layer count enables most flexible format for different ground and power planes. Available in bare die, AISiC Lid, or low cost Flat Lid. Qualified in body sizes ti 45 mm HiTCE (BGA), 45 mm alumina (SCI) and 31 mm alumina (BGA).
Applications:
The fcCSP package is targeted to high-performace workstations, servers, data communication products, internet routers and at high frequency and RF packaging applications where electrical performance is critical. The elimination of wirebond loops allows for a low inductance connection to the die, while the increased routing density enables optimized electrical paths for critical high frequency signal lines. The fcCSP is also an attractive option for portable and handheld electronics where, in addition to performance, package size is critical.
Features:
- Designed for high frequency applications
- 49 - 1800 Ball Counts
- Target Market - Cell Phones, Handheld Electronics
- Array strip production, overmold + singulate
- Combine with multipile die and or passives
- Thin core laminate or ceramic package construction
- Overmolded for handling and second level reliability
- Accommodates package sizes from 3 mm to 15 mm
- Flip Chip bump pitches of 150 µm min. for peripheral array, 250 µm min. for area array
- Available in 0.5 mm - 1.0 mm BGA ball pitch, as well as LGA interconnect
- Minimum package thickness of 0.80 mm for LGA interconnect, 1.0 mm for 0.5 mm BGA pitch, 1.2 mm for 0.8 mm pitch
- Turnkey Solution - Design, bumping, bumped wafer probe, backgrind, assembly, test
- Much better signal to noise ratio at higher frequencies (>1GHz)
- Low inductance of flip chip bumps - short, direct signal path
- Flexible customized substrate routing
Thermal Performance:
Theta JA (°CW)
- 8 x 8 mm, 64 lead package with 1.75 mm x 2.27 mm die, 0.8 mm pitch, 0.6 mm mold cap
- 0 LFPM, 4 layer PC board
- Junction ambient thermal resistance = 48.1 °C/W
Electrical:
8 x 8 mm body, 64 ld, 0.8 mm ball pitch
Simulated results @ at 100 MHz
| |
Min. |
Max. |
| Inductance |
0.26 nH |
2.16 nH |
| Capacitance |
0.18 pF |
0.38 pF |
| Resistance |
7 m |
53.9 m |
Reliability:
Package Level:
| Laminate moisture sensitivity: |
JEDEC Level 3 @ 240°C 30°C / 60% RH, 192 hours |
| Ceramic moisture sensitivity: |
JEDEC Level 1 @ 260°C 85°C / 85% RH, 168 hours |
| PCT: |
121°C / 100% RH, 96 hours |
| Temp / Humidity: |
85°C / 85% RH, 1000 hours |
| High temp storage: |
150°C, 1000 hours |
| Temp cycle: |
-55°C / +125°C, 1000 cycles |
Board Level:
| Thermal cycle: |
-40°C / +125°C, 1 cycle / hour, 3000 cycles* |
| Thermal cycle: |
-40°C / +125°C, 2 cycles/hour, 2500 cycles* |
*Data for 8 x 8 mm body, 64 lead, 0.33 mm PWB NSMD pad size
Process Highlights:
| Die size (max): |
Pkg size - 1 mm |
| Bump pitch (min): |
Pkg size - 1 mm |
| In-line: |
150 µm |
| Minimum array: |
250 µm |
Standard Materials:
| Package Substrate: |
Hitachi FR5 E679 / BT |
| Bump: |
63 / 37 Sn / Pb |
| Encapsulant: |
Epoxy mold compound |
| Solder balls: |
Eutectic SnPb |
Test Services:
- Program generation / conversion
- Product engineering
- Wafer sort
- -55 °C to +165 °C test available
- Burn-in
Shipping:
- JEDEC trays
- Tape and reel services
Additional Information:
| Description |
File Type |
File Size |
| fcCSP Data Sheet |
|
120 kb
|
Flip Chip Packaging Technology Solution
Sheet |
 |
318 kb |
| Flip Chip Packaging of Low-K Devices |
 |
58 kb |
For more information on the fcCSP package, please contact an Amkor Regional Sales Office near you, your Account Manager or fill out the Request for Additional Information Form. |
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