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Package Stackable etCSP (PS-etCSP / PSCSP / CSP-on-CSP)
(XFXBGA / VFBGA / LFBGA)
 Amkor's PS-etCSP package
is a POP capable of stacking another 0.5 mm pitch package.
This package can squeeze into applications requiring a thin form factor. The
PS-etCSP package is constructed using conventional IC processing including standard wire bonding,
molding and substrate infrastructure. The resulting package consists of three to four peripheral rows of
solder balls to achieve around 300 I/Os.
Applications:
Amkor's PS-etCSP design makes this package type ideal for ASIC IDMs, memory vendors such as NOR, NAND, SDRAM, cell phones and handsets, digital still camera and digital camcorder, mid-range consumer products, portable gaming and other portable products where vertical
height is limited. Because of the unique design of the PS-etCSP package, stacking is easily achieved
with proper substrate designs. This creates an opportunity to multiply memory capacity without
increasing board area.
Features:
- Around 200 - 300 I/Os available
- 300 I/O count is available by full cavity substrate PS-etCSP with 0.5 mm pitch, 3 or 4 rows
- 9 - 14 mm Body size planned
- Known Good Device by individual testing prior to stack
- 1.2 mm by et stacked on PS-etCSP
- 1.4 mm mounting height by CABGA / Stacked CSP stacked on PS-etCSP
- Conventional process flow with proven wirebond technology
- MRT JEDEC Level 1 Reliability to 260°C reflow temperature
- Standardized footprints at 0.5 mm pitch
- Two stacked die potential
- Compatible with SMT process
- A variety of CSP-on-CSP configurations to meet customers applications
Thermal Performance:
Amkor’s initial PS-etCSP® packages are offered for low power applications. Higher thermal performance can be achieved by adding a heat spreader or heat sink to the die's exposed backside. In addition, future die-up configurations will provide a direct heat dissipation path into the product motherboard through the die backside.
Electrical Performance:
| |
Min |
Max |
| Inductance (nH) |
0.735 |
1.546 |
| Capacitance (pF) |
0.176 |
0.319 |
| Resistance (mOhms) |
47.9 |
89.83 |
Package Dimensions:
7 x 7 mm body; 89 I/O; 0.3 mm ball diameter; 100 MHz
Reliability:
| Moisture sensitivity: |
JEDEC Level 1 @ 260°C |
| Temp / Humidity: |
85°C / 85% RH, 1000 hrs |
| PCT / HAST: |
130°C, 85% RH, 96 hrs |
| High temp storage: |
150°C, 1000 hrs |
| Temp cycle: |
-55°C / +125°C, 1000 cycles |
Process Highlights:
| Die Thickness (max): |
150µm |
| Wire bonding: |
Standard; low loop |
| Die attach adhesive: |
Not required |
| Package marking: |
Laser |
Standard Materials:
| Package substrate: |
Thin core FR5 or equivalent |
| Au wire: |
20 µm diameter |
| Encapsulant: |
Standard EMC |
| Solder balls: |
0.3 mm dia. 63Sn / 37Pb & SnAgCu |
Shipping:
PS-etCSP packages are shipped in JEDEC trays or in tape and reel if final electrical testing is performed.
Additional Information:
| Description |
File Type |
File Size |
| etCSP® Data Sheet |
|
147 kb
|
| PSvfBGA Data Sheet |
|
502 kb
|
| Stacked CSP Data Sheet |
|
204 kb
|
| 3D Technology Solution Sheet |
|
204 kb
|
| "Stacked Package-on-Package Design Guidelines " By Moody Dreiza, Akito Yoshida, Jonathan Micksch and Lee Smith,, Amkor Technology Inc. This article originally appeared in Chips Scale Review Magazine, July 2005 |
|
124 kb
|
For more information on the PS-etCSP package or Amkor's Package-on-Package technology, please contact an Amkor Regional Sales Office near you, your Account Manager or fill out the Request for Additional Information Form. |
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