Level Fan-Out (WLFO) is a package technology designed to provide
increased I/O density within a reduced footprint and profile for low
density single die and multi die applications at lower costs. Most
recently, WLFO is experiencing increased interest due to its ability to
also integrate mid ranged I/O density die into three dimensional reduced
form factors. Amkor has developed the capability to produce both single
die and multi die Wafer Level Fan-Out packages, including 3D
Amkor has taken a conservative but strategic approach in developing its wafer level fan-out technologies. This has proven to be beneficial from both an economical and technical standpoint. First, Amkor adapted existing bump and assembly equipment to create its baseline 200mm Wafer Level Fan-Out platform. Amkor then supplemented these existing assets with readily available 200mm systems from external sources. This has resulted in a cost-effective and extendable WLFO bump and assembly platform for initial process and package development. This “invest smart” strategy has allowed Amkor to minimize capital expenditures while advancing the emerging Wafer Level Fan-Out packaging technology to support the demands of high performance mobile and networking devices. In addition, Amkor has been able to optimize its Wafer Level Fan-Out process technology and assembly yields on the smaller and the more robust 200mm format before moving to a more capital intensive and challenging 300mm or panel-based infrastructure.
timing of Amkor’s entrance into wafer level fan-out packaging is also a
crucial part of its overall business strategy. Engagements with key
alpha customers in strategic market segments will allow Amkor to support
a wide range of products as applications arise in the mobile and
networking arena, including Amkor’s single die one-layer RDL package.
This baseline structure is targeted to support mobile data modems, power
management ICs, CODECs, RF switches, and power amplifiers for mobile
devices. WLFO provides improvement in form factor, interconnect density,
and electrical performance.
In addition to establishing a strong technical and business platform for single die wafer level fan-out, Amkor is extending the single die configuration to accommodate increasingly desired advanced 3D structures. Amkor’s key enabling technologies, such as Through-Mold Via™ (TMV®), Chip-on-Chip (CoC), and Fine Pitch Copper Pillar (FP CuP), extend the single die wafer level fan-out application space beyond simple 2D structures. For example, TMV® provides the most space efficient interconnect for unique 3D Wafer Level Fan-Out products such as sensing devices, where miniaturization is critical for mobile applications. Amkor’s first WLFO sensing device is scheduled to go into production in 2013.
TMV® is also one of the
key enabling technologies to create Wafer Level Fan-Out
Package-on-Package (PoP) structures, resulting in significant z-height
reduction, improved electrical performance, and a higher level of
package integration due to the intrinsic benefits brought to the
industry by wafer level fan-out.
Finally, CoC, coupled with FP CuP, allows memory and logic devices to be attached face-to-face in a POSSUM™ wafer level fan-out structure, providing the most efficient low-latency electrical interconnect for mobile computing and networking applications. Amkor’s first POSSUM™ WLFO logic-memory networking device will be qualified for release to production in 2013.
Amkor’s rapid development cycle, robust assembly platform, and quick time to market continue to provide a path to rapid return on its Wafer Level Fan-Out investment.