Wafer Bumping. The electrical and mechanical connection between a die and substrate is one of the most critical elements of any flip chip package structure. Predominantly lead-tin and lead-free solders at the present time, these connections - or bumps - must exhibit superior adhesion to the die, minimal resistance, and result in high assembly yields. Solder bumps are formed by using either thin film metal deposition or ball loading techniques.

Amkor offers state-of-the-art capability in electroplated solder technologies in multiple strategic locations (Korea, China and Taiwan). These locations are uniquely situated adjacent to major foundry sources to enable our customers reduced time-to-market with integrated factory logistics.

Our Taiwan facility is a world-class wafer solder bumping line with HVM production capability for 200mm and 300mm wafers. Eutectic, and lead-free solder compositions (all low alpha) are production certified. In addition, the facility offers repassivation, single-and multi-layer redistribution processes for both flip chip and wafer level chipscale package (WLCSP) applications.

Our Korea, China and Taiwan wafer bumping operations are co-located with wafer probe, assembly and final test, enabling Amkor to provide complete "Turnkey" flip chip and WLCSP solutions in these key geographic locations. These facilities offer economy of scale as WL-CSP continues to grow in the future. This combination of technology and manufacturing capabilities is unparalleled in the subcontract manufacturing industry.

Bumping Process Specifics

Amkor’s wafer bumping process is production certified through the full package size range from WLCSP, up through SuperFC®.

Wafer Size:200 mm,  300 mm
Solder Compositions:63Sn / 37Pb, 95Pb / 5Sn, 97.7Sn / 2.3Ag, 98.25n / 1.8Ag
(All available as low alpha: <0.002 cts / hr / cm2), SnAgCu
Pad Pitch Lower Limit:50 µm
Typical Production Bump Height:150 µm array: 70 µm
125 µm peripheral: 75 µm
Repassivation Coatings:Polyimide, PBO
Redistribution Materials:Copper (Cu)


Related Wafer Bumping Processes / Services

Wafer Bumping and Wafer Level Chip Scale Packaging (WLCSP) use many of the same basic process steps in production. Key WLCSP developments have resulted in improved wafer level technology known as CSPnl. CSPnl combines plated copper technology and advanced photopolymers to produce the industry’s most robust wafer level solutions. CSPnl is available down to 0.3 mm pitch and supports a range of solder volumes to meet customer requirements.

Closely related to both wafer bumping and Wafer Level Packaging (WLP) production is "die processing" capability, which consists of process steps that transform either bumped or WLCSP product from wafer form into die form. Die processing typically involves test, singulation, inspection, and pick-and-place, and Amkor offers these full turnkey services to support our customers at multiple facilities around the world.

Wafer Bumping Technology Development

Amkor maintains strong initiatives in the area of technology development to further support customers’ future needs. Continuous improvement programs are in place to optimize and cost-reduce the wafer bumping processes.

  • Electroplating capabilities will support fine pitch bumping and copper pillar structures
  • Higher performance passivation materials
  • WLCSP die size support to greater than 144 I/O’s and 0.3mm pitch


Amkor’s technology leadership continues to advance flip chip technology as part of our broad portfolio of over 1000 packages. We will continue to partner with leading companies to bring new flip chip products quickly to market. We have the vision and breadth to move flip chip interconnect off the drawing board and into production across a wide range of package formats.

For more information on our Wafer Bumping Processes and Die Level Interconnect Technology services, please contact an Amkor Regional Sales Office near you or fill out the Request for Information Form.

Turnkey Services