The roles of IC packaging substrate are mainly to provide signal transmission, power distribution and heat dissipation between the IC and PWB board (or Component of system) and to act as a space transformer between the fine line dimensions of the IC and the coarse line dimensions of the PWB board.     

Substrate and IC Packaging


Substrate Technology Development Direction

Current key semiconductor packaging requirements are cost competitiveness, miniaturization, better warpage performance, better form factor and higher electrical & thermal performance.  Amkor is underway to continue the substrate-related research and development in order to respond to above market trends and semiconductor packaging requirements. Fig-2 is a chart showing Amkor key substrate technology development directions.

Substrate roadmap

Cost

In general, substrate cost occupies a large percentage of total package price.  Therefore, cost effective substrate development will be a key enabler to develop cost effective packages.  Recent key development directions for cost effective substrate are to replace SOP(solder on pad) substrate with BOL(bond on lead) substrate, to reduce substrate layer count (ex. 4 layer to 3 layer conversion), and to develop lower cost fine line/space patterning methodology like ETS (embedded trace substrate).

Substrate BOL ETS Cross Section

Circuit Density

In order to respond to Si node evolution, finer bump pitch requirements and better bandwidth requirements on the market, higher circuit density technologies like primer- SAP, ABF-SAP, ETS  (embedded trace substrate) and PID (Photo-imageable dielectric) have been developed and used.  Below are its line/space capability to each patterning methodology.

  • Primer-SAP:  12/12um line/space or less
  • ABF-SAP:  9/12um line/space or less
  • ETS:  10/10um line/space or less
  • PID:  5/5m line/space or less

Core/SR material

Recently, one of key customer requirements is better package warpage performance to get better PoP stacking yield or better board mounting yield.  Generally, in order to get better high -temperature warpage performance, lower CTE & higher Tg core materials (≤3.5ppm CTE, ≥300? Tg) and SR materials (≤40ppm CTE, ≥130? Tg) have been developed and used.   


Form Factor

Thin substrate development has been driven by mobile products like application processor and baseband devices, by wearable products like SIP module and by memory products.  For this, thin core materials which are ≤60um in thickness and prepreg / ABF materials which are ≤25um in thickness, or coreless substrates have been developed and used.  And, for package X, Y size reduction, EDS (embedded die in substrate, Fig-5.) technology has been considered and being developed, especially for SIP module.  In general, EDS package can enable us to achieve 20~40% package X, Y size reduction.


Electrical Performance and Thermal Performance

For better electrical performance, low loss substrate solutions like low Df dielectric material and lower Ra trace surface technology have been developed and used.  Recently, core material having 0.004 Df@60GHz was developed and started to be used for some customer high frequency devices requiring higher electrical performance.  And, lower Ra trace surface substrate has also been developed and used recently for network communication FCBGA packages as a low loss solution (Fig-7.).  And, for mobile application processor, EPS (embedded passive in substrate, Fig-6.) which has shorter electrical paths between application processor IC chip and capacitor than normal non-EPS substrate has been used for several years for better clock speed of flagship smart phones in the market.  And, recently thermally enhanced core and prepreg materials featuring around 3 W/mk thermal conductivity are being developed to meet future potential substrate thermal conductivity requirements.

Substrate EDS EPS Cross Section

Substrate Trace

Packaging



Sign Up to Receive
Updates From Amkor
For Email Marketing you can trust