Through silicon via (TSV) interconnects are emerging to serve a wide range of 3D packaging applications and 3DIC (3D IC) architectures that demand higher levels of performance and silicon integration. To enable the use of TSVs in these 3D applications, a number of back-end technology platforms are being developed or deployed for high volume processing.
- Wafer support bond and de-bonding
- TSV based wafer thinning
- Through Silicon Via reveal
- Back side Passivation
- Redistribution
- Micro-bumping
- Thin / high density TSV & micro-bump wafer probe
- TSV based thin wafer handling and dicing
- Thinned die flip chip bonding
- Thinned die flip chip stacking
- Green, low stress material sets
Amkor’s Role in 3D Packaging with TSV Interconnects
Amkor is focused on developing technology solutions for the back end processing of Through Silicon Via (TSV) based wafers, also referred to as wafer finishing, and 3DIC architectures assemblies. This requires skilled capability in the key areas:
Wafer support bond and de-bonding (200 - 300 mm wafers)
- TTV < 5µm
- Wafer thinning to 50µm
- TSV reveal
- Back side Passivation and TSV Isolation
- Back side redistribution
- Micro-bumping
Advanced wafer finishing technology capabilities:
- 200-300 mm wafer support system (WSS)
- Thinning for Copper and Tungsten TSVs
- Can support wafer processing of incoming wafer with and w/out FC bumps
- Ni Au pad finish for die requiring mixed assembly flip chip plus wirebond
- Can receive finished Silicon Interposers or provide the finishing services
- Development to 20μm pitch for micro-bumps
Advanced assembly technology capabilities:
- Flip chip stacking of thin TSV micro-bumped die
- Die to substrate Flip Chip attach
- Die to die Flip Chip micro stacking
- Die to wafer
For more information on our Through Silicon Via (TSV) Wafer Finishing & Flip Chip Stacking Solutions, please contact an Amkor Regional Sales Office near you or fill out the Request Form.
