Flip Chip Technology Overview

Benefits of Flip Chip Technology

• Reduced signal inductance - Because the interconnect is MUCH shorter in length (0.1 mm vs 1-5 mm), the inductance of the signal path is greatly reduced. This is a key factor in high speed communication and switching devices
• Reduced power / ground inductance - By using flip chip interconnect, power can be brought directly into the core of the die, rather than having to be routed to the edges. This greatly decreases the noise of the core power, improving performance of the silicon
• Higher signal density - The entire surface of the die can be used for interconnect, rather than just the edges. This is similar to the comparison between QFP and BGA packages. Because flip chip can connect over the surface of the die, it can support vastly larger numbers of interconnects on the same die size
• Die shrink - For pad limited die (die where size is determined by the edge space required for bond pads), the size of the die can be reduced, saving silicon cost
• Reduced package footprint - In some cases, the total package size can be reduced using flip chip. This can be achieved by either reducing the die to package edge requirements, since no extra space is required for wires, or in utilizing higher density substrate technology, which allows for reduced package pitch

Wafer Bumping Technology

In support of Flip Chip assembly, Amkor has established wafer bumping production lines within their Korea, Taiwan and China manufacturing facilities. Amkor’s bumping is based on its proprietary electroplating solder technology which is considered the most advanced, robust, reliable and high yielding process available in the marketplace. Eutectic Sn/Pb, Pb Free (98.2% Sn/1.8% Ag) and Cu Pillar bumping are all available in volume production on 200 mm and 300 mm wafers.

Features:

• Wafer sizes from 150 mm to 300 mm diameter
• Full area array pitch available to 130 μm -- perimeter pad pitch to < 100 μm
• Eutectic Sn/Pb and Pb Free (98.2Sn / 1.8Ag) compositions available
• Low alpha (< 0.02 cph) and ultralow alpha (<0.002 cph) solders available
• Polyimide repassivation available
• Redistribution layer using plated Cu (Copper) available

Packaging Options Using Flip Chip

Depending on the specific die and application requirements, different package level solutions are required. Thus flip chip interconnect can be used in a wide range of package solutions, each focused on specific benefits that serve a given market. Amkor offers the widest possible range of flip chip packaging solutions to meet the diverse needs of customers and end users. Combining their extensive manufacturing knowledge with all types of packaging interposers and further leveraging their leadership role in flip chip interconnect technology, Amkor continues to pursue new package solutions. This kind of focus is essential to insure that as new market needs emerge requiring flip chip interconnect, Amkor is ready with the optimum package to meet those needs.

Flip Chip BGA Package:

fcBGA Technology Options:

• Substrates
  • 4-16 layer laminate build up substrates
  • High CTE ceramic
  • LTCC Alumina ceramic
  • Coreless (in development)
• Bump Types
  • Eutectic Sn/Pb
  • Pb Free
  • Cu Pillar (array and fine pitch peripheral)
• Package Formats
• Bare Die
• Overmolded (FCMBGA)
• Lidded
• 150 μm minimum array bump pitch (130 μm in development)
• <100 μm minimum peripheral bump pitch
• Die sizes up to 26 mm
• Package sizes from 10 mm to 55 mm
• 0.65 mm, 0.8 mm, and 1.0 mm pitch BGA footprints

 
fcBGA Additional Package Options:

• Wafer Node: ≥ 28 nm qualified (20nm in development)
• SMT components on top or bottom side
• Multi-Die capability
• Memory components on top side
• Variety of lid material options
• Grounded lid
• Custom BGA footprints

fcCSP Package:

Flip chip solution for CSP package technology.

fcCSP Features:

• Designed for high frequency applications
• Target market – cell phones, hand-held electronics
• Thin core laminate or ceramic package construction
• Overmolded for handling and second level reliability
• Accommodates package sizes from 3 mm to 15 mm
• Flip chip bump pitches of 150 μm min. for peripheral array, 250 μm min. for area array
• Available in 0.5-1.0 mm BGA ball pitch, as well as LGA interconnect
• Minimum package thickness of 0.80 mm for LGA interconnect, 1.0 mm for 0.5 mm BGA pitch and 1.2 mm for 0.8 mm BGA pitch

Flip Chip SiP (fcSiP) Package:

Flip Chip SiP package is an extension of the SiP product offering from Amkor with the device interconnect technology being flip chip rather than traditional wirebond interconnects. The package may contain multiple passive components, Silicon and/or GaAs devices bumped with traditional solder bumps or solder coated 'Copper-Pillar' bumps housed in 2-Layer or 4-Layer high density substrates. This package format is gaining traction in RF power amplifier and RF front end module applications for size, performance and cost reasons.

Controlled collapse of the bumps leads to predictable interconnect impedance and hence more stable product performance. The low solder volume in the 'wetting tip' allows for the elimination of the solder mask from underneath the die which reduces the substrate complexity and cost and removes a major barrier for adopting the fine pitch FC interconnection technology in the RF application space. Flip chip interconnection may also preclude the need for wafer backgrinding (for mold cap thickness ≥ 0.9 mm) which leads to further reduction in product cost and simplification of the process flow.

The devices in this application space have low to medium I/O count and are fairly small in size. This, in conjunction with the solder mask being removed from underneath the die (which increases the standoff), makes these products viable candidates for transfer molding applications. Thus, the underfill operation can be eliminated from the process flow which leads to significant cost savings. Studies have shown that transfer molded packages are more reliable (MSL as well as extended reliability testing such as temperature cycling, HAST, etc.) than their underfilled counterparts due to balanced die stresses and better solder CTE matching.

Wafer Level Packaging (WLP) - CSPnl:

CSPnl is a true wafer level package to address improved second level board reliability, that incorporates a thin film redistribution process to route the pads to JEDEC standard pitches. Standard "CSP" solder bumps are formed on the re-routed pads. The CSPnl is designed to utilize standard surface mount assembly and reflow techniques. By using standard SMT placement equipment, and avoiding the need for underfill, the end user experiences many of the cost benefits associated with other JEDEC standard area array packages.

Features:

• Incorporates standard JEDEC pitches and CSP solder ball diameters
• Compatible with standard SMT assembly and test techniques
• Utilizes cost-effective thin film redistribution technologies
• Backside laser mark compatible
• No need for underfill in most applications
• Full turnkey CSPnl™processing including test and tape & reel support
• Eutectic lead-free solder balls
• Available with polyimide repassivation
• Qualified and in volume production
• Proven reliability; exceeds all current handset mechanical reliability tests including: drop, bend and key punch

FCMBGA (Flip Chip Molded BGA)

FCMBGA is the evolution of the SuperFC® high performance flip chip olution. Capillary Underfill (CUF) is replaced by Molded Underfill (MUF).

fcBGA / fcLGA (Bare Die)

Flip chip packaging solution for most graphics, PC chipset and low end ASIC applications.

fcCeramic CBGA / CLGA / CLLGA / Solder Column Interposer

Original packaging solution for flip chip products.

Wafer Bumping Technology:

In support of Flip Chip assembly, Amkor has established wafer bumping production lines within their Korea, Taiwan and China manufacturing facilities. Amkor’s bumping is based on its proprietary electroplating solder technology which is considered the most advanced, robust, reliable and high yielding process available in the marketplace. Eutectic Sn/Pb, Pb Free (98.2% Sn/1.8% Ag) and Cu Pillar bumping are all available in volume production on 200 mm and 300 mm wafers.

Features:

• Wafer sizes from 150 mm to 300 mm diameter
• Full area array pitch available to 130 μm -- perimeter pad pitch to < 100 μm
• Eutectic Sn/Pb and Pb Free (98.2Sn / 1.8Ag) compositions available
• Low alpha (< 0.02 cph) and ultralow alpha (<0.002 cph) solders available
• Polyimide repassivation available
• Redistribution layer using plated Cu (Copper) available