Flip chip interconnect utilizes array interconnect of die to substrate as a replacement for conventional wire bonding. This allows the entire die surface to be used for electrical connections to the substrate, exponentially increasing the I/O per unit area vs. perimeter interconnect technologies. Using flip chip interconnect improves package electrical performance by removing the high inductance wires and replacing them with low inductance solder connections. Flip chip interconnect also allows highly parallel, direct connection with on-die power planes, which enables performance at lower operating voltages. Amkor FCBGA packages are assembled around state?of?the?art, single unit laminate or ceramic substrates.
Utilizing multiple high density routing layers, laser drilled blind, buried, and stacked vias, and ultra fine line/space metallization, FCBGA substrates have the highest routing density available. By combining flip chip interconnect with ultra advanced substrate technology, FCBGA packages can be electrically tuned for maximum electrical performance. Once the electrical function is defined, the design flexibility enabled by flip chip also allows for significant options in final package design. Amkor offers FCBGA packaging in a variety of product formats to fit a wide range of end application requirements.
This IC packaging technology is applicable for high pincount and / or high performance ASICs. Large body fcBGAs provide package solutions for the demands of internet, workstation processors and high bandwidth system communication devices. By incorporating flip chip interconnect technology, packages supporting thousands of connections are enabled in onventional surface mount package sizes. fcBGAs are also the package of choice for aming system processors and graphics, as well as high-end applications processors for eading-edge portable devices.
The variety of FCBGA package options allows package selection to be tailored to the specific thermal needs of the end product. High performance ASIC products typically utilize a Lidded format that features a controlled bondline die attach direct to a copper heat spreader. This feature produces the lowest possible thermal resistance (Theta JC) between the package and any externally applied thermal solution. The copper heat spreader effectively spreads heat laterally away from the die to the package perimeter and into the motherboard.
Lower wattage products generally utilize Bare Die or Molded configurations. In these cases, the flip chip construction, with solder bumps and core vias, provides a lower resistance path from the active side of the die through the substrate, allowing heat dissipation both from the package surface and into the motherboard.
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The product is shipped in standard JEDEC trays