Amkor offers Wafer Level Chip Scale Packaging (WLCSP) providing a solder interconnection directly between your device and your end product’s motherboard. WLCSP includes wafer bumping (with or without pad layer redistiribution or RDL), wafer level final test, device singulation and packing in tape & reel to support a full turn?key solution. Amkor’s robust Under Bump Metallurgy (UBM) over PBO or PI dielectric layers on the die active surface providing a reliable interconnect solution able to survive harsh board level conditions meeting the demands of the growing global consumer market place for portable electronics.

Fueling Growth

  • Small packages in mobile critical to maximize battery size
  • Level of adoption in fastest growing markets (i.e., tablets and smartphones)
  • Dis-integration of high performance functions from processors to new specialized devices(e.g., audio)
  • Fewer cycles through electrical test
  • Lower cost to EMS assembly MSL L1 package from T&R
  • Improved SMT-compatible underfill processes at EMS companies increase prior die size limits


Three WLCSP options are offered

  • The CSPnl Bump on Repassivation (BoR) option provides a reliable, cost-effective, true chip-size package on devices not requiring redistribution. The BoR option utilizes a repassivation polymer layer with excellent electrical/mechanical properties. A UBM is added, and solder bumps are then placed directly over die I/O pads. CSPnl is designed to utilize industry-standard surface mount assembly and reflow techniques.

  • The CSPnl Bump on Redistribution (RDL) option adds a plated copper Redistribution Layer (RDL) to route I/O pads to JEDEC/EIAJ standard pitches, avoiding the need to redesign legacy parts for CSP applications. A nickelbased or thick copper UBM offerings, along with polyimide or PBO dielectrics, provide best in class board level reliability performance. CSPnl with RDL utilizes industry-standard surface mount assembly and reflow techniques, and does not require underfill on qualified device size and I/O layouts.

  • CSPn3 option utilizes one layer of copper for both redistribution and UBM. This simplified process flow reduces cost and cycle time by over 20%. CSPn3 has been in production since 2009 and as of 2012 is at a run rate of over 1 billion units annualized.

 

WLCSP Applications

The WLCSP package family is applicable for a wide range of semiconductor device types from high end RF WLAN combo chips, to FPGAs, power management, Flash/EEPROM, integrated passive networks and standard analog. WLCSP offers the lowest total cost of ownership enabling higher semiconductor content while leveraging the smallest form factor and one of the highest performing, most reliable, semiconductor package platforms on the market today. WLCSP is ideally suited for, but not limited to, mobile phones, tablets, netbook PCs, disk drives, digital still & video cameras, navigation devices, game controllers, other portable/remote products and some automotive end applications.

WLCSP Features

  • 4 - 196 ball count
  • Small body 0.64mm2 to large 50.0 mm2 body size
  • PBO & Polyimide (PI) Repassivation and Redistribution Layer (RDL) available
  • Electroplated Sn/Ag < 0.3 μm and SAC Alloy ball-loaded bumping options ≥ 0.3 μm pitch
  • Reliable thick Cu UBM or Ni/Au for best in class EM performance
  • Compatible with conventional SMT assembly and test techniques


Die Level Features

  • Best in class component and board level reliability
  • JEDEC tested board level performance demonstrated without underfill
  • Precision edge quality ensuring device integrity at board mount
  • Back-side laminate coating available
  • Cost effective T&R packaging solutions for small ICs
  • Ultra-thin backgrinding for embedded die applications
  • Full turnkey WLP, contact probe and DPS supported in Taiwan, China and Korea
  • Wide selection of pocket tape carrier options

 

WLCSP Package Level Reliability:

Preconditioning at Level 1
(Unlimited out of bag life)
  -55°C / +125°C, 1000 cycles
High Temp Storage:   150°C, 1000 hours
Moisture Resistance:
   MSL1



WLCSP Second Level Reliability (BLR):

Temp Cycling:   -40°C / +125°C, 15 min. ramp rate, >500 cycles
Drop Test:   JEDEC condition B (1500G), >100 Drops

 

WLCSP Capabilities and Services

Design:

  • Layout
  • Mask tooling


WLP Manufacturing:

  • Wafer RDL patterning and bumping (ball sphere loaded or plated)
  • Automated Optical Inspection (AOI) for best in class quality assurance
  • Wafer map generation


Test:


Die Processing (DPS) Integration and Support:

  • Backgrind
  • Backside Lamination
  • Laser Mark
  • Singulation
  • Tape & Reel
  • AOI
  • Best in class singulated device edge quality for all Si nodes
  • Shipping material design and supply management
  • Drop ship to final customer available

 

Package Options / Ball Loading:

Pitch  Sphere Diameter 
0.30 mm
  0.20 mm
0.40 mm     0.25 mm  
0.50 mm     0.30 mm  

 

WLCSP Process Highlights

Die thickness:   225 μm* to 450 μm. *Advanced manufacturing rules may be required.
Bump height:   250 µm (0.5 mm pitch), 210 µm (0.4 mm pitch), 170 µm (0.3 mm pitch)
Solder ball pitch (ball loaded):   0.28, 0.3, 0.35, 0.4, 0.5 mm
  Pitch (Plated): 0.12 to 0.25 mm
Solder sphere diameter:   0.2, 0.25, 0.3 mm
Redistribution trace/space (min):   CSPnl: 12/12 μm
  CSPn3: 15/15 μm
 Via diameter (min):  PBO: 15 μm
  Polyimide: 35 μm
 Backside laminate (black)  Available
 Saw street (min)  65 μm (passivation free space)


Standard Materials:

Dielectric material:   Polyimide and PBO
RDL metalization:  Plated copper
UBM:   Thick Cu or Ni-based
Solder Composition  
Ball Loaded:   Pb-free SAC alloys
Plated:   Sn/Ag Pb-free, Cu pillar

Shipping:

Devices are shipped in carrier tape on standard 7” or 13” reels.

WLCSP Cross Sections:

CSPnl BOR

 

 CSPnl RDL

 

CSPn3

For more information on our CSPnl Wafer Level Packaging (WLP / WLCSP), please contact an Amkor Regional Sales Office near you or fill out the Request Form.

Packaging



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