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SuperFC® (Super Flip Chip)

Super Flip Chip SuperFC IC PackageAmkor's SuperFC® is THE high performance flip chip solution. Flip chip interconnect utilizes array interconnect of die to substrate as a replacement for conventional wire bonding. This allows the entire die surface to be used for electrical connections to the substrate, exponentially increasing the I / O per unit area vs. perimeter interconnect technologies. Implementing process technology licenced from industry leader LSI logic, Amkor’s SuperFC® package uses solder bump flip chip interconnect and can route over 1000 signal traces from a single die out to a 1.0 mm pitch BGA footprint.

SuperFC® packages are assembled around state-of-the-art laminate substrates. Utilizing multi-layer, blind and buried vias, laser drilled build up structures, and ultrafine line / space metalization, SuperFC® has the highest routing density available. Using flip chip interconnnect automatically improves package electrical performance by removing the high inductance wires and replacing them with low inductance solder connections. By combining flip chip with ultra advanced substrate technology, packages can be electrically tuned for maximum electrical performance. Amkor has qualified packages using high Tg epoxy as dielectric materials, to provide the maximum flexibility in package price / performance offerings.

Applications:

This IC packaging technology is applicable for high pincount and / or high performance ASICs. It is the current mainstream FlipChip package for ASIC applications. SuperFC® provides the package solution for the demands of internet, workstation processors and high bandwidth system communication devices. By incorporating flip chip interconnect technology, packages supporting thousands of connections are enabled in conventional surface mount package sizes.

Features:

  • 4-10 layer build up substrates
  • Attached 1 or 2 piece heat spreader design for maximum thermal performance
  • 150 µm minimum bump pitch
  • Die sizes up to 26 mm
  • 252-2397 Ball Count
  • Package sizes from 17 mm - 52.5 mm
  • JEDEC MS-034 compliant
  • 1.0 mm pitch BGA footprint

Thermal Performance:

SuperFC® packages feature a controlled bondline die attach direct to a copper heat spreader. This results in the lowest possible thermal impedence between the package and any externally applied thermal solution. The copper heat spreader construction also effectively transmits heat back down through the package into the motherboard. Thermal measurements have shown Theta JC to be < 1°C/W and theta JA to be similar to SuperBGA® products across the body sizes tested.

Reliability:

SuperFC® has consistently passed JEDEC Level 3 245°C (30°C / 60% RH / 192 hrs, 3x reflow, followed by 1 dry 260°C reflow), and has completed Amkor’s internal Level B qualification. Package has been proven to pass industry standard package temperature cycle and temperature / humidity / bias requirements.

Process Highlights:

Die size (max):   26 mm
Bump pitch (min):   150 µm

Standard Materials:

Package Substrate:  
  - Build up laminate  
  - HDI laminate  
D/A:   Proprietary
U/F:   Proprietary
Bumps:   Eutectic, HighPb, Lead Free
Balls:   Eutectic Lead Free
Heat spreader:   1 Piece Ni-plated Copper

Test Services:

Please contact the Test Product Group for details on the services available.

  • Program generation / conversion
  • Product engineering support
  • Available test / handling technology
  • Burn-in

Shipping:

  • The product is shipped in standard JEDEC trays

Additional Information:

Description File Type File Size
  SuperFC® Data Sheet
131 kb
  Flip Chip Packaging Technology Solution
  Sheet
318 kb
  Flip Chip Packaging of Low-K Devices 58 kb

For more information on the SuperFC® package, please contact an Amkor Regional Sales Office near you, your Account Manager or fill out the Request for Additional Information Form.


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