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Stacked CSP (S-CSP)
(Stacked Die / LFBGA / TFBGA)
 The Stacked CSP (S-CSP) family utilizes Amkor's industry leading ChipArray® Ball Grid Array (CABGA) and TapeArray® (TABGA) manufacturing capabilities. This broad high volume infrastructure enables the rapid deployment of advances in die stacking technology across multiple products and factories to achieve lowest total cost requirements.
Stacked CSP technology enables the stacking of a wide range of different semiconductor devices to deliver the high level of silicon integration and area efficiency required in portable multi-media products. Stacked CSP uses high density thin core substrates, advanced wafer thinning, die attach, flip chip and wire bonding capabilities to stack multiple devices in a conventional fine pitch BGA (FBGA) surface mount component. These advanced assembly capabilities in combination with Amkor's expertise in design and test, enable stacks up to 5 active devices without sacrificing yield or mounted height requirements.
Many customers have relied on Amkor to solve their highest density and most complex device stack combinations. As a result, Amkor has established industry leadership in stacking complex mixed signal, logic + memory devices, including digital base band or applications processors + high density flash or mobile DRAM devices. Designers are looking to Stacked CSP technologies to achieve integration, size and cost reductions in future chip set combinations.
Applications:
Portable multi-media devices including cell phones, digital cameras, PDAs, audio players and mobile gaming employ S-CSP solutions to address a range of design requirements, including:
- Higher memory capacity
- More complex and efficient memory architectures
- Smaller, lighter and more innovative new product form factors
- Lower cost
Features:
- 5 - 17 mm body size
- Package height down to 0.8 mm
- 44 - 400+ ball count available
- Design, assembly and test capabilities that enable stacking of DRAM with Logic or Flash memory devices
- Logic / Flash, Digita l/ Analog and other ASIC / Memory combinations of 320 I/O and greater
- Pb free, RoHS compliant and Green materials
- Passive component integration options
- Established package infrastructure with standard CABGA footprints
- Consistent product performance high yields and reliability
- JEDEC Standard Outlines including MO-192 and MO-219
- Thin spacer technology
- Die overhang wire bonding
- Low loop wire bonding less than 75 µm
- Wafer thinning / handling to 75 and 50 µm
Reliability:
Amkor assures a reliable performance by continuously monitoring key indices:
Package Level:
| Moisture Resistance Testing: |
JEDEC Level 3 @ 260°C |
| Additional Test Data at: |
[ (30°C / 85% RH / 96hrs) + 260 ] x2 or 3 |
| Unbiased Autoclave/PCT: |
121°C / 100% RH / 2atm, 168 hours |
| Temp / Humidity: |
85°C / 85% RH / 1000 hours |
| High temp storage: |
150°C, 1000 hours |
| Temp cycle: |
-55 / +125°C, 1000 cycles |
Board Level:
| Thermal cycle: |
-40 / +125°C, 1000 cycles |
Process Highlights:
| Die qty, stack: |
Up to 5 high die configurations |
| Ball pad pitch: |
0.4, 0.5, 0.65, 0.75, 0.8 mm |
| Die thickness (min): |
Down to 50 µm |
| Laminate core thickness: |
60, 100 or 150 µm |
| Ball diameter: |
0.25, 0.3, 0.4, 0.46 mm |
| Die bond pitch (min): |
40 µm (In-line) with roadmap to 25 µm |
| Wirebond length (max): |
5 mm (200 mils) |
| Wirebond dia (min): |
18, 20, 25, 30 µm |
| Wafer thinning: |
200 & 300 mm wafers |
Standard Materials:
| Package Substrate |
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| - Layer count (Laminate): |
2-4 |
- Dielectric:
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Laminate (e.g., E679, BT), Polyimide (e.g., Kapton®) |
| Device type: |
Silicon, SiGe, etc. |
| Die attach |
|
| - (Bottom die): |
Silver Filled Epoxy |
| - (Top die): |
Non-conductive Epoxy or Elastomeric Film |
| Wire type, Gold: |
High tensile |
| Encapsulant: |
Liquid Epoxy (Black) |
| Solderball: |
63Sn / 37Pb & PbFree Sn/3-4Ag / 0.5Cu |
| Marking: |
Laser |
Contact Amkor for Daisy chain sample availability and the latest S-CSP capabilities.
Additional Information:
| Description |
File Type |
File Size |
| Stacked CSP Data Sheet |
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204 kb
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| Stacked CSP Data Sheet (Japanese Translation) |
|
355 kb
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| PSvfBGA Data Sheet |
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502 kb
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| 3D Technology Solution Sheet |
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284 kb
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| "Stacked-Chip-Scale-Package Design Guidelines” By Moody Dreiza, Amkor Technology, Inc. and Mark Gerber, Texas Instruments. This article originally appeared in EDN Magazine, June 8, 2006 |
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For more information on the Stacked CSP package, please contact an Amkor Regional Sales Office near you, your Account Manager or fill out the Request for Additional Information Form.
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