After 3 years of development in package stacking technology and infrastructure, Amkor launched the multiple award winning PSvfBGA (base PoP) platform during the 4th quarter of 2004. The next two years saw many new milestones, from publication of JEDEC mechanical and electrical standards to a range of new customers and applications adopting PoP. By the end of 2006 PSvfBGA became the fastest growing new product in Amkor's history, reflecting the broad industry benefits of PoP and Amkor's leadership position. The next few years promise to provide many new challenges and applications for PoP, as handheld multimedia applications continue to demand higher processing power and memory storage capacities. Amkor is committed to maintain strong development and production capabilities to ensure we are forefront in meeting next generation PoP requirements.

Amkor has expanded our comprehensive PoP family and aligned the roadmap across the supply chain to ensure that PoP will continue to scale with the industry's miniaturization, higher density and performance enhancement requirements.

In 2006 Amkor's PoP family ramped products with 2 die stacked in the PSvfBGA platform. Stacking multiple die in the bottom package allows customers to increase performance and provide further system miniaturization by combining analog + digital or logic + memory devices.

Contact Amkor for Daisy Chain sample availability, the latest PSvfBGA capabilities, and for full review of PSvfBGA, PoP technology and roadmaps.

Applications:

PoP packages are designed for products requiring efficient memory architectures including multiple buses and increased memory density & performance, while reducing mounted area. Portable electronic products such as mobile phones (baseband or applications processor + combo memory), digital cameras (image processor + memory), PDAs, portable players (audio / graphics processor + memory), gaming and other mobile applications can benefit from the combination of stacked package and small footprint offered by Amkor's industry leading PoP family.

Broad Benefits as an Enabling Technology:

PoP provides OEMs and EMS providers with a platform to cost effectively expand options for logic + memory 3D integration with the following benefits:

• Greatly expands device options by simplifying the business logistics of stacking
• Integration controlled at the system level to best match stacked combinations with system requirements
• JEDEC standards ensure broad component availability
• Eliminates margin stacking and expands technology reuse
• Helps manage the huge cost impacts associated with increasing demand for multi-media processing and memory
• Logic device transitions to flip chip in the bottom package enables further PoP size and height reductions

Features:

• 10-15 mm body sizes planned per product table. Additional sizes based on demand
• Top package I/O interface 0.65 mm pitch accommodating 104 to 160 pin counts
• High I/O 0.50 mm pitch interface is qualified
• Fine pitch 0.50 mm bottom package footprints with 0.40 mm pitch in qualification
• Established package on package infrastructure (Over 5 years of development with leading OEM, EMS and equipment providers)
• Wafer thinning / handling < 100 µm
• Consistent product performance and reliability
• Package configurations compliant with JEDEC standards
• Package pre-stacking support and services available based on demand
• Bottom PSvfBGA and top FBGA / Stacked CSP packages are well established in high volume production
• Stacked package heights of 1.2 mm to 1.6 mm available in a variety of configurations. (See Stack Up table below)

Mechanical Samples:

For mechanical samples of our PSvfBGA (Package-on-Package) package, please click here. Contact Practical Components for the PoP (PSvfBGA) Drop Test Board and Kit.

PoP Overall Stack Up Table

Reliability:

Amkor assures a reliable performance by continuously monitoring key indices:

Process Highlights:

Standard Materials:

Test Services:

Shipping:

• Tape and reel services
• JEDEC trays

• Dimensions are in line with JEDEC JC-11 standards for PoP packages in development
• Assuming 2 perimerter rows of interconnects at 0.65 mm pitch
• Assuming 4 perimeter rows of BGA balls to motherboard at 0.50 pitch

Additional Information:

Description	File Type	File Size
PSvfBGA Data Sheet		502 kb
PSvfBGA Dual Sided Test Contactor Data Sheet		131 kb
Stacked CSP Data Sheet		204 kb
3D Technology Solution Sheet		204 kb
"Study on the Board Level Reliability Test of Package on Package (PoP) with 2nd Level Underfill” By Moody Dreiza, Amkor Technology. Presented at the 2007 ECTC; June, 2007		912 kb
"High Density PoP (Package-on-Package) and Package Stacking Development” By Moody Dreiza & Akito Yoshida, Amkor Technology; Kazuo Ishibashi, Nokia; Tadashi Maeda, Panasonic. Presented at the 2007 ECTC; June, 2007		1.8 MB
"Package-on-Package: The Story Behind This Industry Hit” By Lee Smith, Amkor Technology, Inc. This article originally appeared in Semiconductor International Magazine, June, 2007
"A Study on Package Stacking Process for Package-on-Package (PoP)" By Akito Yoshida and Jun Taniguchi, Amkor Technology Inc. This White Paper originally appeared at ECTC 2006		322 kb
"Package on Package (PoP) | Stacking and Board Level Reliability, Results of Joint Industry Study" By Moody Dreiza, Amkor Technology Inc. This White Paper originally appeared at IMAPS 2006, March 23, 2006		577 kb
"Stacked Package-on-Package Design Guidelines" By Moody Dreiza, Akito Yoshida, Jonathan Micksch and Lee Smith, Amkor Technology Inc. This article originally appeared in Chips Scale Review Magazine, July 2005		124 kb

For more information on the PSvfBGA, S-PSvfBGA package or Amkor's Package-on-Package (PoP) technology, please contact an Amkor Regional Sales Office near you, your Account Manager or fill out the Request for Additional Information Form.